{"created":"2023-06-19T10:29:35.472654+00:00","id":9515,"links":{},"metadata":{"_buckets":{"deposit":"cdb1a5e7-2b88-4cba-8b99-d05ceb67cbc6"},"_deposit":{"created_by":18,"id":"9515","owners":[18],"pid":{"revision_id":0,"type":"depid","value":"9515"},"status":"published"},"_oai":{"id":"oai:muroran-it.repo.nii.ac.jp:00009515","sets":["216:292","46"]},"author_link":["4713"],"item_79_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2016-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"309","bibliographicPageEnd":"176","bibliographicPageStart":"173","bibliographicVolumeNumber":"116","bibliographic_titles":[{"bibliographic_title":"電子情報通信学会技術研究報告","bibliographic_titleLang":"ja"},{"bibliographic_title":"IEICE Technical Report","bibliographic_titleLang":"en"}]}]},"item_79_description_7":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"マイクロ波シミュレーションにターゲットを絞ることにより,汎用アーキテクチャ故にPC等で生じていた無駄な処理をなくし,低コスト,小型,かつ低消費電力な高性能計算を実現すべく,著者らはデータフローアーキテクチャ方式に基づいたFDTD法/FIT専用計算機の開発を行ってきた.専用計算機の開発に際しては,とりわけ,計算性能を重視した検討が中心となり,実際,FDTD法専用計算機でも,ハイエンドPCやGPUを越える性能が発揮できることが示されているものの,その一方で,幅広い応用や大規模計算などの検討も実用利用に際しては必須の課題となる.本研究では,専用計算機の実用利用を目指した場合におけるもっとも大きな課題の一つである大規模計算実現のための領域分割法の実装を検討したので報告する.","subitem_description_language":"ja","subitem_description_type":"Abstract"},{"subitem_description":"To aim achieve a high-performance computation for microwave simulations with low cost, small size machine and low energy consumption, author has been working in development of the FDTD method dedicated computer with dataflow architecture. It was shown by VHDL logical circuit simulations of the FDTD machine that the designed architecture has much higher performance than that of high-end PC and GPU. However it was also found that microwave simulation for only 25 x 25 grid space in x-y plane can be executed in a single FPGA at most. To treat much larger numerical model size for practical applications, this paper considers implementation of a domain decomposition method operation of the FDTD dedicated computer in single FPGA.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_79_link_5":{"attribute_name":"室蘭工業大学研究者データベースへのリンク","attribute_value_mlt":[{"subitem_link_text":"川口 秀樹（KAWAGUCHI Hideki）","subitem_link_url":"http://rdsoran.muroran-it.ac.jp/html/100000127_ja.html"}]},"item_79_publisher_11":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"電子情報通信学会","subitem_publisher_language":"ja"}]},"item_79_rights_19":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright © IEICE 2016","subitem_rights_language":"en"}]},"item_79_source_id_12":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0913-5685","subitem_source_identifier_type":"PISSN"},{"subitem_source_identifier":"2432-6380","subitem_source_identifier_type":"EISSN"}]},"item_79_subject_9":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"541.2","subitem_subject_scheme":"NDC"}]},"item_79_version_type_21":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorAffiliations":[{"affiliationNameIdentifiers":[{}],"affiliationNames":[{},{}]}],"creatorNames":[{"creatorName":"KAWAGUCHI,  Hideki","creatorNameLang":"en"},{"creatorName":"川口,  秀樹","creatorNameLang":"ja"},{"creatorName":"カワグチ, ヒデキ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-09-28"}],"displaytype":"detail","filename":"IEICE_116(309)_173.pdf","filesize":[{"value":"419.9 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"IEICE_116(309)_173","objectType":"fulltext","url":"https://muroran-it.repo.nii.ac.jp/record/9515/files/IEICE_116(309)_173.pdf"},"version_id":"c88fe6e3-7c9c-46a9-9708-d4f19b992d68"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"マイクロ波シミュレーション","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"FDTD法","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"FIT","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"専用計算機","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"ハイパフォーマンスコンピューティング","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"データフローアーキテクチャ","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject":"領域分割法","subitem_subject_language":"ja","subitem_subject_scheme":"Other"},{"subitem_subject_scheme":"Other"},{"subitem_subject":"Microwave simulation","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"FDTD method","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"FIT","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Dedicated computer","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"High-performance computing","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Dataflow architecture","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"Domain-decomposition method","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"データフローアーキテクチャFDTD法/FIT専用計算機における領域分割法の実装に関する研究","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"データフローアーキテクチャFDTD法/FIT専用計算機における領域分割法の実装に関する研究","subitem_title_language":"ja"},{"subitem_title":"Design Study of Domain Decomposition Operation in Dataflow Architecture FDTD/FIT Dedicated Computer","subitem_title_language":"en"}]},"item_type_id":"79","owner":"18","path":["46","292"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2017-09-28"},"publish_date":"2017-09-28","publish_status":"0","recid":"9515","relation_version_is_last":true,"title":["データフローアーキテクチャFDTD法/FIT専用計算機における領域分割法の実装に関する研究"],"weko_creator_id":"18","weko_shared_id":-1},"updated":"2023-10-16T07:04:11.846279+00:00"}